Aging Monitoring Methodology for Built-In Self-Test Applications

The high integration level, complexity and performance achieved in new nanometer technologies make IC (Integrated Circuits) products very difficult to test. Moreover, long-term operation brings aging cumulative degradations, and new processes and materials lead to emerging defect phenomena. The consequence is obtaining products with increased variability in their behavior, more susceptible to delay faults and with reduced expected lifecycle. The main purpose of this work is twofold, as explained in the following. First, a new software tool is presented to generate HDL (Hardware Description Language) BIST (Built-In Self-Test) structures, aiming delay faults, and insert the new auto-test functionality in generic sequential CMOS circuits. The BIST methodology used implements a scan based BIST approach, using a new BIST controller to implement the delay-fault techniques Launch-On-Shift (LOS) and Launch-On-Capture (LOC). Second, it will be shown that multi-VDD tests in circuits with BIST infra-structures can be used to detect gross delay faults during on-field operations, and consequently can be used as an aging sensor methodology during circuits’ lifecycle. The discrete set of multi-VDD BIST sessions generates a Voltage Signature Collection (VSC), and the presence of a delayfault (or a physical defect) modifies the VSC collection, allowing the aging sensor capability. The proposed Design for Testability (DFT) method and tool are demonstrated with extensive SPICE simulations using benchmark circuits.